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C8254 Programmable Timer/Counter Megafunction
Introduction
The C8254 programmable interval timer/counter megafunction is a high-performance device, which is designed to solve the common timing control problems in microcomputer system design. It provides three independent 16-bit counters, and each counter may operate in a different mode. All modes are software programmable. Six programmable timer modes allow the device to be used as an event counter, elapsed time indicator, programmable one-shot, and in many other applications.
Symbol
Features
* Three Independent 16-bit Counters Status Read-Back Command Counter Latch Command Read/Write LSB only or MSB only or LSB first then MSB Six Programmable Counter Modes o o o o o o * * * Interrupt on Terminal Count Hardware Retriggerable One-Shot Rate Generator Square Wave Mode Software Triggered Strobe Hardware Triggered Strobe (Retriggerable) * * * *
ADDR[1:0] DIN[7:0] CSN RDN DOUT[7:0] WRN OUT0 CLK0 OUT1 GATE0 OUT2 CLK1 GATE1 CLK2 GATE2 RESETN C8254
Binary or BCD Counting Also available in VHDL or Verilog Functionality based on the INTEL 8254
Applications
The six programmable timer modes allow the C8254 to be used in applications requiring event counters, elapsed time indicators, and programmable one-shots among others.
CAST, Inc.
March 2004
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CAST C8254 Megafunction Datasheet
Pin Description
Name DIN[7:0] ADDR[1:0] CSN RDN WRN RESETN CLK0 GATE0 CLK1 GATE1 CLK2 GATE2 OUT0 OUT1 OUT2 DOUT[7:0] Type In In In In In In In In In In In In Out Out Out Out Polarity Low Low Low Low Falling Falling Falling Description Data Bus Input Address Chip Select Read Control Write Control Reset internal Registers Clock input of Counter 0 Gate input of Counter 0 Clock input of Counter 1 Gate input of Counter 1 Clock input of Counter 2 Gate input of Counter 2 Output of Counter 0 Output of Counter 1 Output of Counter 2 Data Bus Output
Block Diagram
DIN[7:0]
Data Bus Buffer
CLK0 Counter 0 GATE0 OUT0
DOUT[7:0] RDN WRN CSN ADDR[1:0] RESETN Program Read and Write Logic
CLK1 Counter 1 GATE1 OUT1
Counter Read/Write Control & Control Word Register
CLK2 Counter 2 GATE2 OUT2
Figure 1 - Block Diagram
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CAST C8254 Megafunction Datasheet
Functional Description
This section provides a short description of each element of the Block Diagram (Figure 1).
Data Bus Buffer
8-bit input and output data bus buffer is used to interface the C8254 to the system bus.
Read/Write Logic
The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the C8254. ADDR[1:0}select one of the three counters or the control word register to be read from or written into. A "low" on RDN tells the C8254 that the CPU is reading one of the counters. A "low" on the WRN input tells the C8254 that the CPU is writing either a Control Word or an initial count. Both RDN and WRN are qualified by CSN. RDN and WRN are ignored unless the C8254 has been selected by holding CSN "low".
Control Word Register
The Control Word Register is selected by the Read/Write Logic when ADDR[1:0] = 11. During writing, the data is stored in the Control Word Register and it is interpreted as a Control Word used to define the operation of the Counters. Control Word Format D7 SC1 SC1 0 0 1 1 RW1 0 0 1 1 M2 0 0 X X 1 1 BCD 0 1 D6 SC0 SC0 0 1 0 1 RW0 0 1 0 1 M1 0 0 1 1 0 0 M0 0 1 0 1 0 1 D5 RW1 D4 RW0 D3 M2 D2 M1 D1 M0 D0 BCD
Select Counter 0 Select Counter 1 Select Counter 2 Read-Back Command Counter Latch Command Read/Write LSB only Read/Write MSB only Read/Write LSB first, then MSB Mode Mode Mode Mode Mode Mode 0 1 2 3 4 5
Binary Counter 16-bits BCD Counter (4 Decades)
CAST, Inc.
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CAST C8254 Megafunction Datasheet
Read/Write Control
Upper/Lower Byte Controller
Control Word MSB-CNTREG CRM LSB-CNTREG CRL
16-Bit Counter CE16 Control Logic 8-Bit Status Register
16-Bit Output Latch OLREG
CLK# OUT# GATE#
Upper/Lower Byte Controller
Read Counter Controller
Figure 2 - Internal Counter Block Diagram
Counter 0, Counter 1, Counter 2
These three functional blocks are identical in operation, so only a single Counter will be described. The internal block diagram of a single counter is shown in Figure 2. The Counters are fully independent. Each Counter may operate in a different Mode.
Control Logic
This block controls the 16-bit counter for all counting modes and the Null flag of the counter.
Upper/Lower Byte Controller
The width of the data bus is 8 bits, and the counter is 16 bits. The Upper/Lower Byte Controller allows one 8bit Counter Register, MSB or LSB, to be loaded one at a time from the internal bus. If the Counter is programmed for two-byte read/write mode, this block will control which data byte will be read at the next read cycle.
Counter Registers
There are two 8-bit registers called CRM and CRL. Both are normally referred to as one unit and called just CR. When a new count is written to the Counter, the count is stored in the CR and later transferred to the CE16. At the rising-edge of WRN, it will write data to the register. One register at a time will be allowed to be loaded from the internal bus. After both registers have been loaded, both bytes are transferred to the CE16 simultaneously. CRM and CRL are cleared when the Counter is programmed. Note that the CE16 can't be written into; whenever a count is written, it is written into the CR.
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CAST C8254 Megafunction Datasheet
16-Bit Counter
This block contains a 16-bit Binary or BCD presettable synchronous down counter.
8-Bit Status Register
The 8-bit Status Register contains the Control Word Register, the status of the output and null count flag. When there is a Read-Back Command with STATUSN bit enabled and its counter selected, it will latch present status information into Status Register. The status format is shown below: D7 Out D6 Null Count D5 RW1 D4 RW0 D3 M2 D2 M1 D1 M0 D0 BCD
Bits D5 through D0 contain the counter's programmed Mode. Output bit D7 contains the current state of the OUT pin. This allows the user to monitor the counter's output via software. Null Count bit D6 indicates when the last count written to the counter register has been loaded into the counting element (CE16). The exact time this happens depends on the Mode of the counter.
8-Bit Output Latch Register
At the time of receiving the Counter Latch Command or Read-Back Command with COUNTN bit enabled, the selected counter's output latch latches the count. This count is held in the latch until the CPU reads it or until the counter is reprogrammed. The count is then unlatched and the OL returns to be transparent of counting element outputs. The count must be read according to the programmed format. The Counter Latch Command is ignored before the count is read.
Read Counter
If both the count and the status of a counter are latched, the first read operation of that counter will return the latched status, regardless of which was latched first. The next one or two reads (depending on whether the counter is programmed for one or two byte counts) returns the latched count. Subsequent reads return the unlatched count. If the counter is programmed for two byte counts, it will read the LSB first then the MSB at the next read cycle.
Verification Methods
The C8254 megafunction's functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Intel 82C54 chip, and the results compared with the megafunction's simulation output
Device Utilization & Performance
Supported Family Cyclone Stratix Stratix-II Device Tested EP1C20-6 EP1S20-5 EP2S60-3 LEs 524 524 536 Utilization Memory Memory bits 0 0 0 0 0 0 Performance Fmax 109 MHz 119 MHz 166 MHz
CAST, Inc.
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CAST C8254 Megafunction Datasheet
Deliverables
Netlist License
* * * * * * * * * * * *
Post-synthesis EDIF netlist Assignment & Configuration Symbol & Include files Testbench (self checking) Vectors & expected results for testing functionality Documentation
HDL Source License
VHDL or Verilog RTL source code Testbenches (self checking) Wrapper for pin compatible replacement Vectors & expected results for testing functionality Synthesis and simulation scripts Documentation
Related Information
Intel Microprocessor and Peripheral Handbook 1989 Volume II - Microprocessor ISBN: 1-55512-041-5
Contact Information
CAST, Inc. 11 Stonewall Court Woodcliff Lake, New Jersey 07677 USA Phone: +1 201-391-8300 Fax: +1 201-391-8694 E-Mail: info@cast-inc.com URL: www.cast-inc.com
Copyright (c) CAST, Inc. 2004, All Rights Reserved. Contents subject to change without notice.
CAST, Inc.
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